The overall array architecture for a typical integrated circuit containing a memory includes a core memory, herein referred to as a core, and input/output circuitry, herein referred to as the periphery. The core generally contains a plurality of core cells (i.e. individual memory elements) that are arranged in an array of rows and columns. The core cells store at least one bit of data and are accessed through the periphery to external elements, such as a microprocessor, which require the data.
When the core is accessed, the microprocessor or other external element requests data stored in the core. Power is consumed both reading the data from the core to the periphery and driving the data onto the bus connecting the periphery and microprocessor. In general, there is a constant need to decrease the amount of power consumed while providing more powerful and faster elements and circuitry. Either decreasing the power used by individual components or minimizing the power used by the entire access process decreases the power used in retrieving sets of data from the core (either individual sets of bits, words or bytes, depending on the arrangement) and driving the sets of data along the bus to be read by a microprocessor or other external elements.
Thus, it is desirable to produce arrangements in which the power consumption is reduced. For example, large amounts of power are consumed when driving retrieved data along the bus dependent on the dynamical changes between successive sets of data being driven. This is to say that, power is consumed when data occupying a position on the bus (say data 0 occupying position 1) and being driven along the bus during one clock cycle changes states (say data 1 occupying position 1) and is driven along the bus during the next clock cycle. If the data occupying a particular position on the bus does not change from one clock cycle to the next clock cycle, significantly less power is consumed.
It is desirable to produce an arrangement in which the power consumption is reduced when driving successive sets of data to the bus, thereby increasing battery lifetime in portable computers, for example. In general, however, it is also desirable to increase the speed accessing data from the core, especially with the huge increase in the speed of microprocessors (and other external elements). Typically, the amount of time required to access data from the core is limited by the throughput of the accessing circuitry (usually limited by clocking the data through several subsections of the accessing circuitry). Thus, it is beneficial to produce an arrangement or method in which both the power consumption and throughput are decreased.